A semiconductor device manufacturing method includes a process (pillar head exposing process) of exposing the upper surface of a pillar from an insulating layer after the pillar is formed on a base layer and buried in the insulating layer. The problem of this process is that the timing at which the upper surface of the pillar is exposed cannot be detected when exposing the upper surface of the pillar from the insulating layer by CMP (Chemical Mechanical Polishing) or etch back. Therefore, it is conventionally necessary to combine CMP, RIE (Reactive Ion Etching), IBE (Ion Beam Etching), and the like, or obtain an optimal etching time by verifying the relationship between the etching time of the insulating layer and the exposed state (the etching amount of the insulating layer) of the upper surface of the pillar by using samples.